1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device that includes a memory cell array including a plurality of memory cells each including a variable resistive element which stores information by shifting between a plurality of states an electric resistance of a variable resistor sandwiched between a first electrode and a second electrode, by applying a voltage pulse between the first electrode and the second electrode.
2. Description of the Related Art
In portable electronics devices or mobile devices, a volatile memory such as a low-cost DRAM having a small number of parts and a nonvolatile memory such as a large-capacity and low-cost flash memory are being used, as a main storage memory into which a CPU (Central Processing Unit) can directly perform a write process and a read process. The main storage memory into which a CPU directly performs a write process and a read process is required to be able to realize the write process and the read process at a high speed to shorten a processing time, and is also required to have high reliability with few errors in writing and reading, for usage of the main storage memory. The main storage memory is also required to have small power consumption to extend a using time of an electronics device, and is required to be highly integrated along with downsizing of electronics devices and mobile devices.
Because a volatile memory such as a DRAM requires a refresh operation, reduction of power consumption is difficult, and a using time of electronics devices is limited. Further, a nonvolatile memory such as a flash memory has a problem in its high integration because of a limit to miniaturization. Therefore, there are being progressed development of an MRAM (Magneto-resistive Random Access Memory), a PCRAM (Phase-Change Random Access Memory), a CBRAM (Conductive-Bridging Random Access Memory), and an RRAM (Resistive Random Access Memory) that uses a variable resistive element.
In this case, the RRAM is expected as a promising main storage memory, because the RRAM has a large resistance change and a high-speed write process can be performed, because a random access to a memory cell array is possible, because a constituent material is a binary material that has high affinity with a CMOS process, and because a memory structure is simple and high integration is possible.
The RRAM includes a variable resistive element which is formed by sandwiching a variable resistor between a first electrode and a second electrode, and stores information by shifting an electric resistance of the variable resistor between a plurality of states, by applying a voltage pulse between the first electrode and the second electrode. A write process and a read process of the RRAM are controlled by magnitude of a voltage value of a voltage pulse. Therefore, to prevent an erroneous writing and an erroneous reading, it is desirable that there is a sufficient difference between a voltage value of a voltage pulse that is used in the write process and a voltage value of a voltage pulse that is used in the read process.
However, along with miniaturization and integration in a semiconductor process, a voltage value of a power supply voltage tends to become small. Therefore, a write voltage and a write current that are used for the write process are also required to be reduced. Further, to realize a high-speed read process, it is difficult to reduce a read current that is used for the read process. Therefore, it becomes difficult to secure a sufficient difference between the write voltage and the read voltage. That is, along with miniaturization and integration of elements, when it is not possible to secure a sufficient difference between the write voltage and the read voltage, there is a problem in that a risk of occurrence of an erroneous writing and an erroneous reading becomes high.
Further, along with an increase in capacity, the number of variable resistive elements to be mounted increases, and the number of circuits that receive an unintended load such as a leak current increases. Therefore, there is a risk of occurrence of an erroneous writing. When a read process is continuously performed to a specific memory cell at a considerable number of times, a resistance state of a variable resistor changes due to a read voltage that is applied in the read process, and there is a risk of occurrence of an erroneous reading. That is, the RRAM is also required to have a technology of preventing an erroneous writing and an erroneous reading, in a similar manner to that of other memories.
In the main storage memory, to secure reliability by preventing an erroneous writing and an erroneous reading, an error detection process is conventionally performed (refer to Japanese Patent Application Laid-open Publication No. 2008-27296, for example (hereinafter, “Publicly Known Document 1”)).
According to Publicly Known Document 1, both a databank that stores data and an ECC bank that stores an error correction code are configured in the same memory device. With this arrangement, a processing time is shortened, as compared with a case that a databank and an ECC bank are built in different memory devices.
When an RRAM is used for a main storage memory into which the CPU directly performs writing and reading of data, reliability is very important. Therefore, it is desirable to perform an error detection and correction process in high precision, by using a Reed-Solomon code, for example. However, an error detection and correction process in high precision that uses a Reed-Solomon code tends to take a long time for the error detection and correction process, and there is a risk of increasing a time required for the write process and the read process.
In particular, in the RRAM, a speed of a data write process is faster than that in other memories. Therefore, a time required for the error correction and detection process gives a large influence to a processing speed of an overall write process and to a processing speed of an overall read process. Accordingly, shortening of a time required for the error detection and correction process is more desired.
According to the memory device in Publicly Known Document 1, a processing time is shortened, by configuring both the databank and the ECC bank in the same memory device, from a viewpoint of shortening an access time to the memory device. However, further shortening of the processing time is required.